Advances have been made in metal oxide semiconductor field effect transistors (MOSFETs). One design consideration is the on-resistance of the transistor as compared to the area of the device.
FIG. 2 shows a top-view photograph of an array 10 of cells 12 of a prior art silicon carbide SiC double-implanted MOSFET (DMOSFET). More specifically, the array includes a plurality of interdigitated source fingers 14 and gate fingers 16. FIG. 1 shows a schematic cross-sectional view of a cell 12 (and part of another cell) of the array 10 including one gate finger 16 and parts of two source fingers 14. As shown in FIG. 1a, the DMOSFET cell 12 includes a drain contact layer, e.g., a nickel layer 20, a substrate 22, a drift region 24, a base region 26, a source region 28, a source contact 30, a conductive gate 32, a gate insulator 34, and a top contact layer 36.
The substrate 22 is an SiC substrate of a first dopant type (N+) having a high dopant concentration. The drift region 24 is also of the first dopant type, but has a lower dopant concentration (N−), less than the first high concentration. The base region 26 comprises implanted wells of a second dopant type, e.g., a P− base. The source regions 28 are also of the first dopant type and have a high concentration, e.g., N+ source regions. The gate finger 16 defines a gate region that includes the gate insulator 34, which may be an oxide region, and the conductive gate 32, which may suitably be a polysilicon gate. The top metal contact layer 36 directly abuts the source contact 30 and the gate insulator 34. The top metal contact layer 36 provides an electrical connection to the source contact 30. The top metal contact layer 36 is electrically insulated from the gate 32 by the gate insulator 34.
In operation, when a voltage is applied to the gate conductor 32, an inversion layer is formed near the top of the p-base region 26, and an n-type accumulation layer is formed near the top of the drift region 24. As a result current flows between the source and draining via the source region, the inversion layer in the P-base region 26, the drift region 24, and the semiconductor substrate 22.
While only one portion of the DMOSFET is shown in FIG. 1a, it is understood that these portions duplicate in a repeated fashion, as shown in FIG. 2.
One performance metric for power MOSFETs is the specific on-resistance, defined as the product of device area and device resistance in the linear region. Several factors contribute to the specific on-resistance, but the most important are (i) channel resistance, (ii) source resistance, (iii) JFET resistance (i.e. resistance of the portion of the drift region that lies between the P base regions), (iv) drift region resistance, and (v) drain resistance.
While the above design provides for relatively advantageous on-resistance characteristics, new designs are needed to lessen resistance-area product of a MOS devices by reducing on-resistance, device area, or both.